library ieee; 
use ieee.std_logic_1164.all;
--use ieee.std_logic_unsigned.all;

entity SHIFT_REG_TEST is
end;

architecture TESTBENCHS of SHIFT_REG_TEST is
 component SHIFT_REG
 port (
    I    : in std_logic_vector(7 downto 0);
    SI, CLK, LOAD, SHIFT  : in std_logic;
    O    : out std_logic_vector(7 downto 0);
    SO   : out std_logic
 );
 end component;
 signal t_si,t_clk,t_l,t_sh,t_so:std_logic;
 signal t_i,t_o:std_logic_vector(7 downto 0);
begin
 i_shr: SHIFT_REG port map(
  I=>t_i,SI=>t_si,CLK=>t_clk,LOAD=>t_l,
  SHIFT=>t_sh,O=>t_o,SO=>t_so
 );
 tst_clk:process
 begin
  t_CLK<='0';
  wait for 20 ns;
  t_CLK<='1';
  wait for 20 ns;
 end process;
 tst:process
 begin
  t_i<="10110111";
  t_l<='1';
  t_sh<='0';
  t_si<='0';
  wait for 40 ns;
  assert t_o = "10110111"
  report "nepodarilo se ulozit"  
  severity failure;
  t_l<='0';
  wait for 40 ns;
  assert t_o = "10110111"
  report "nepodarilo se vydrzet"  
  severity failure;
  t_sh<='1';
  wait for 40 ns;
  assert t_o & t_so= "010110111"
  report "nepodarilo se posunout"  
  severity failure;
  t_si<='1';
  wait for 40 ns;
  assert t_o & t_so= "101011011"
  report "nepodarilo se cin"  
  severity failure;
  wait ;
end process;
end ;