library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned."-"; entity COUNTER is generic (n:integer:=3); port ( I : in std_logic_vector(n-1 downto 0); LOAD,CE,CLK:in std_logic; ZERO : out std_logic ); end ; architecture COUNTER of COUNTER is signal s:std_logic_vector(n-1 downto 0); begin P1:process begin if CLK='1' then if LOAD='1' then s<=I; elsif CE='1' then s<=s - "001"; end if; wait for 0 ns; if s = "000" then ZERO<='1' after 10 ns; else ZERO<='0' after 10 ns; end if; end if; wait on CLK; end process; end ;