library ieee; 

use ieee.std_logic_1164.all;

entity eAND is
  port (
    SEL: in std_logic;
    A : in std_logic_vector(7 downto 0);
    Y : out std_logic_vector(7 downto 0)
  );
end eAND;

architecture eAND of eAND is 
begin
  P1:process(A,SEL)
  begin
   L1:for i in A'RANGE loop
    Y(i)<=A(i) and SEL after 10 ns;
   end loop;
 end process;
end ;